Plan 9 from Bell Labs’s /usr/web/sources/patch/sorry/ahciupd2/diff

Copyright © 2021 Plan 9 Foundation.
Distributed under the MIT License.
Download the Plan 9 distribution.


3c3
<  * copyright © 2007 coraid, inc.
---
>  * copyright © 2007-8 coraid, inc.
19a20
> #define	Ticks		MACHP(0)->ticks
40a42
> 	Tunk,
43c45
< #define Intel(x)	((x) == Tesb  || (x) == Tich)
---
> #define Intel(x)	((x)->pci->vid == 0x8086)
48a51
> 	"ahci",
154c157
< static	int	debug;
---
> static	int	debug = 0;
762c765
< 	if((s & 0xF00) != 0x600)
---
> 	if((s & 0x700) != 0x600)
804c807
< 	if((p->sstatus & 0xF0F) == 0x601) /* drive coming up in slumbering? */
---
> 	if((p->sstatus & 0x707) == 0x601) /* drive coming up in slumbering? */
843c846
< ahciconf(Ctlr *ctlr)
---
> ahciconf(Ctlr *c)
848c851
< 	h = ctlr->hba = (Ahba*)ctlr->mmio;
---
> 	h = c->hba = (Ahba*)c->mmio;
854,856c857,859
< 	print("#S/sd%c: ahci: port %#p: hba sss %ld; ncs %ld; coal %ld; "
< 		"mports %ld; led %ld; clo %ld; ems %ld\n",
< 		ctlr->sdev->idno, h,
---
> 	print("#S/sd%c: ahci %s port %#p: sss %ld ncs %ld coal %ld "
> 		"mports %ld led %ld clo %ld ems %ld\n",
> 		c->sdev->idno, Tname(c), h,
928,929c931
< 	if((osectors == 0 || osectors != s) &&
< 	    memcmp(oserial, d->serial, sizeof oserial) != 0){
---
> 	if(osectors != s || memcmp(oserial, d->serial, sizeof oserial)){
995c997
< 			if((p->sstatus & 0xF00) == 0x600)
---
> 			if((p->sstatus & 0x700) == 0x600)
1077c1079
< 	if(stat != 3){		/* device absent or phy not communicating? */
---
> 
1079,1083d1080
< 		d->state = Dportreset;
< 		iunlock(d);
< 		return;
< 	}
< 	ilock(d);
1092c1089,1094
< 	qlock(&d->portm);
---
> 	if(stat != 3){		/* device absent or phy not communicating? */
> 		ilock(d);
> 		d->state = Dportreset;
> 		iunlock(d);
> 		return;
> 	}
1093a1096
> 	qlock(&d->portm);
1174,1175c1177,1178
< 	    TK2MS(MACHP(0)->ticks - d->intick) > 5000){
< 		dprint("%s: drive hung; resetting [%lux] ci=%lx\n",
---
> 	    TK2MS(Ticks-d->intick) > 5000){
> 		dprint("%s: drive hung; resetting [%lux] ci=%lux\n",
1199a1203
> /* drive must be locked */
1200a1205,1219
> statechange(Drive *d)
> {
> 	switch(d->state){
> 	case Dnull:
> //	case Dmissing:
> 	case Doffline:
> 		if(d->unit->sectors != 0){
> 			d->sectors = 0;
> 			d->mediachange = 1;
> 		}
> 	}
> 	d->wait = 0;
> }
> 
> static void
1210c1229
< 		d->lastseen = MACHP(0)->ticks;
---
> 		d->lastseen = Ticks;
1295a1315
> 	statechange(d);
1549c1569
< 		δ = MACHP(0)->ticks - d->lastseen;
---
> 		δ = Ticks-d->lastseen;
1572a1593
> loop:
1574c1595
< 	while ((i = waitready(d)) == 1) {
---
> 	if((i = waitready(d)) == 1){
1577c1598
< 		qlock(&d->portm);
---
> 		goto loop;
1621d1641
< 	d->active++;
1640c1660,1661
< 	d->intick = MACHP(0)->ticks;
---
> 	d->intick = Ticks;
> 	d->active++;
1646a1668
> 	d->active--;
1653c1675
< 		d->port->ci = 0;		/* clearci? */
---
> 		d->port->ci = 0;
1658d1679
< 	d->active--;
1737d1757
< 		d->active++;
1755c1775,1776
< 		d->intick = MACHP(0)->ticks;
---
> 		d->intick = Ticks;
> 		d->active++;
1761a1783
> 		d->active--;
1769c1791
< 			d->port->ci = 0;	/* @? */
---
> 			d->port->ci = 0;
1773d1794
< 		d->active--;
1818a1840
> pcicfgw16(c->pci, 0x92, (1<<6)-1);
1823c1845,1846
< 	pcicfgw8(c->pci, 0x90, 1<<6 | 1<<5);
---
> //	pcicfgw8(c->pci, 0x90, 1<<6 | 1<<5);
> 	pcicfgw16(c->pci, 0x90, 1<<6 | 1<<5);
1844d1866
< 		/* 0x27c4 is the intel 82801 in compatibility (not sata) mode */
1847,1848c1869,1874
< 		else if(p->vid == 0x8086 && p->did == 0x27c5)
< 			type = Tich;	/* 82801g[bh]m; compat mode fails */
---
> 		else if(p->vid == 0x8086 && (p->did & 0xfffe) == 0x27c5)
> 			type = Tich;		/* 82801g[bh]m */
> 		else if(p->vid == 0x8086 && (p->did & 0xfeff) == 0x2829)
> 			type = Tich;		/* ich8 */
> 		else if(p->vid == 0x8086 && (p->did & 0xfffe) == 0x2922)
> 			type = Tich;		/* ich9 */
1851c1877
< 		else
---
> 		else if(p->ccrb != Pcibcstore || p->ccru != 6 || p->ccrp != 1)
1852a1879,1881
> 		else
> 			type = Tunk;		/* i'm feeling lucky */
> 
1879c1908
< 		if(Intel(c->type) && p->did != 0x2681)
---
> 		if(Intel(c) && p->did != 0x2681)
1883c1912
< 		if(Intel(c->type) && iaahcimode(p) == -1)
---
> 		if(Intel(c) && iaahcimode(p) == -1)
1997c2026
< 	t0 = MACHP(0)->ticks;
---
> 	t0 = Ticks;
2000c2029
< 	dprint("flush in %ldms\n", MACHP(0)->ticks - t0);
---
> 	dprint("flush in %ldms\n", Ticks-t0);
2043c2072
< 		i = 0;
---
> 		error(Ebadctl);
2046,2050c2075
< 	if(i == Dnull){
< 		d->mediachange = 1;
< 		if(d->unit)
< 			d->unit->sectors = 0;	/* force disk to disappear. */
< 	}
---
> //	statechange(d);
2144a2170,2190
> struct{
> 	ulong	bit;
> 	char	*name;
> }htab[] = {
> 	Hs64a,	"64a",
> 	Hsalp,	"alp",
> 	Hsam,	"am",
> 	Hsclo,	"clo",
> 	Hcccs,	"coal",
> 	Hems,	"ems",
> 	Hsal,	"led",
> 	Hsmps,	"mps",
> 	Hsncq,	"ncq",
> 	Hssntf,	"ntf",
> 	Hspm,	"pm",
> 	Hpsc,	"pslum",
> 	Hssc,	"slum",
> 	Hsss,	"ss",
> 	Hsxs,	"sxs",
> };
> 
2147c2193
< iartopctl(SDev *sdev, char *p, char *e)
---
> iartopctl(SDev *s, char *p, char *e)
2149d2194
< 	ulong cap;
2151,2152c2196,2198
< 	Ahba *hba;
< 	Ctlr *ctlr;
---
> 	ulong cap, i;
> 	Ahba *h;
> 	Ctlr *c;
2154,2175c2200,2207
< #define has(x, str) if(cap & (x)) p = seprint(p, e, "%s ", (str))
< 
< 	ctlr = sdev->ctlr;
< 	hba = ctlr->hba;
< 	p = seprint(p, e, "sd%c ahci port %#p: ", sdev->idno, hba);
< 	cap = hba->cap;
< 	has(Hs64a, "64a");
< 	has(Hsalp, "alp");
< 	has(Hsam, "am");
< 	has(Hsclo, "clo");
< 	has(Hcccs, "coal");
< 	has(Hems, "ems");
< 	has(Hsal, "led");
< 	has(Hsmps, "mps");
< 	has(Hsncq, "ncq");
< 	has(Hssntf, "ntf");
< 	has(Hspm, "pm");
< 	has(Hpsc, "pslum");
< 	has(Hssc, "slum");
< 	has(Hsss, "ss");
< 	has(Hsxs, "sxs");
< 	portr(pr, pr + sizeof pr, hba->pi);
---
> 	c = s->ctlr;
> 	h = c->hba;
> 	p = seprint(p, e, "sd%c ahci %s port %#p: ", s->idno, Tname(c), h);
> 	cap = h->cap;
> 	for(i = 0; i < nelem(htab); i++)
> 		if(cap&htab[i].bit)
> 			p = seprint(p, e, "%s ", htab[i].name);
> 	portr(pr, pr + sizeof pr, h->pi);
2177c2209
< 		"iss %ld ncs %ld np %ld; ghc %lux isr %lux pi %lux %s ver %lux\n",
---
> 		"iss %ld ncs %ld np %ld ghc %lux isr %lux pi %lux %s ver %lux\n",
2179,2180c2211
< 		hba->ghc, hba->isr, hba->pi, pr, hba->ver);
< #undef has
---
> 		h->ghc, h->isr, h->pi, pr, h->ver);

Bell Labs OSI certified Powered by Plan 9

(Return to Plan 9 Home Page)

Copyright © 2021 Plan 9 Foundation. All Rights Reserved.
Comments to [email protected].