Plan 9 from Bell Labs’s /usr/web/sources/patch/armv7-atomic/readme

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Update ARM atomic operations (tas, cas, casp, xinc/xdec, ainc/adec)
to work correctly on multiprocessors (armv7 and later).  This entails
changing SWPW to LDREX/STREX, and adding DMB barriers.

Also add emulation of DMB to the kw (armv5) kernel, so the new library
routines can still be used with older ARM systems.

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