Plan 9 from Bell Labs’s /usr/web/sources/contrib/stallion/patch/extra/bcm-sources.diff

Copyright © 2021 Plan 9 Foundation.
Distributed under the MIT License.
Download the Plan 9 distribution.


diff -Nru /n/sources/plan9/sys/src/9/bcm/arm.s /sys/src/9/bcm/arm.s
--- /n/sources/plan9/sys/src/9/bcm/arm.s	Fri Dec 28 10:31:55 2012
+++ /sys/src/9/bcm/arm.s	Wed Jul  3 03:25:42 2013
@@ -19,11 +19,11 @@
 
 #define ISB	\
 	MOVW	$0, R0; \
-	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEwait
+	MCR	P(CpSC), 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEwait
 
 #define DSB \
 	MOVW	$0, R0; \
-	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEwait
+	MCR	P(CpSC), 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEwait
 
 #define	BARRIERS	ISB; DSB
 
diff -Nru /n/sources/plan9/sys/src/9/bcm/dat.h /sys/src/9/bcm/dat.h
--- /n/sources/plan9/sys/src/9/bcm/dat.h	Wed May 15 13:16:56 2013
+++ /sys/src/9/bcm/dat.h	Sat Jun 29 23:37:12 2013
@@ -224,7 +224,7 @@
 	Lock;
 	int	machs;			/* bitmap of active CPUs */
 	int	exiting;		/* shutdown */
-	int	ispanic;		/* shutdown in response to a panic */
+	int	panicking;		/* panic */
 }active;
 
 extern register Mach* m;			/* R10 */
diff -Nru /n/sources/plan9/sys/src/9/bcm/fns.h /sys/src/9/bcm/fns.h
--- /n/sources/plan9/sys/src/9/bcm/fns.h	Wed May 14 22:01:41 2014
+++ /sys/src/9/bcm/fns.h	Thu Feb  5 17:42:43 2015
@@ -103,6 +103,7 @@
 
 extern void kexit(Ureg*);
 
+#define	_debug()
 #define	getpgcolor(a)	0
 #define	kmapinval()
 #define countpagerefs(a, b)
diff -Nru /n/sources/plan9/sys/src/9/bcm/l.s /sys/src/9/bcm/l.s
--- /n/sources/plan9/sys/src/9/bcm/l.s	Thu Jan  3 06:17:09 2013
+++ /sys/src/9/bcm/l.s	Wed Jul  3 03:28:23 2013
@@ -25,11 +25,11 @@
 	 * disable the mmu and L1 caches
 	 * invalidate caches and tlb
 	 */
-	MRC	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
+	MRC	P(CpSC), 0, R1, C(CpCONTROL), C(0), CpMainctl
 	BIC	$(CpCdcache|CpCicache|CpCpredict|CpCmmu), R1
-	MCR	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
-	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvu), CpCACHEall
-	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
+	MCR	P(CpSC), 0, R1, C(CpCONTROL), C(0), CpMainctl
+	MCR	P(CpSC), 0, R0, C(CpCACHE), C(CpCACHEinvu), CpCACHEall
+	MCR	P(CpSC), 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
 	ISB
 
 	/*
@@ -54,16 +54,16 @@
 	 * set up domain access control and page table base
 	 */
 	MOVW	$Client, R1
-	MCR	CpSC, 0, R1, C(CpDAC), C(0)
+	MCR	P(CpSC), 0, R1, C(CpDAC), C(0)
 	MOVW	$PADDR(L1), R1
-	MCR	CpSC, 0, R1, C(CpTTB), C(0)
+	MCR	P(CpSC), 0, R1, C(CpTTB), C(0)
 
 	/*
 	 * enable caches, mmu, and high vectors
 	 */
-	MRC	CpSC, 0, R0, C(CpCONTROL), C(0), CpMainctl
+	MRC	P(CpSC), 0, R0, C(CpCONTROL), C(0), CpMainctl
 	ORR	$(CpChv|CpCdcache|CpCicache|CpCmmu), R0
-	MCR	CpSC, 0, R0, C(CpCONTROL), C(0), CpMainctl
+	MCR	P(CpSC), 0, R0, C(CpCONTROL), C(0), CpMainctl
 	ISB
 
 	/*
@@ -79,7 +79,7 @@
 	 * enable cycle counter
 	 */
 	MOVW	$1, R1
-	MCR	CpSC, 0, R1, C(CpSPM), C(CpSPMperf), CpSPMctl
+	MCR	P(CpSC), 0, R1, C(CpSPM), C(CpSPMperf), CpSPMctl
 
 	/*
 	 * call main and loop forever if it returns
@@ -90,19 +90,19 @@
 	BL	_div(SB)		/* hack to load _div, etc. */
 
 TEXT fsrget(SB), 1, $-4				/* data fault status */
-	MRC	CpSC, 0, R0, C(CpFSR), C(0), CpFSRdata
+	MRC	P(CpSC), 0, R0, C(CpFSR), C(0), CpFSRdata
 	RET
 
 TEXT ifsrget(SB), 1, $-4			/* instruction fault status */
-	MRC	CpSC, 0, R0, C(CpFSR), C(0), CpFSRinst
+	MRC	P(CpSC), 0, R0, C(CpFSR), C(0), CpFSRinst
 	RET
 
 TEXT farget(SB), 1, $-4				/* fault address */
-	MRC	CpSC, 0, R0, C(CpFAR), C(0x0)
+	MRC	P(CpSC), 0, R0, C(CpFAR), C(0x0)
 	RET
 
 TEXT lcycles(SB), 1, $-4
-	MRC	CpSC, 0, R0, C(CpSPM), C(CpSPMperf), CpSPMcyc
+	MRC	P(CpSC), 0, R0, C(CpSPM), C(CpSPMperf), CpSPMcyc
 	RET
 
 TEXT splhi(SB), 1, $-4
@@ -183,7 +183,7 @@
 	MOVW	R1, CPSR
 
 	MOVW	$0, R0				/* wait for interrupt */
-	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEintr), CpCACHEwait
+	MCR	P(CpSC), 0, R0, C(CpCACHE), C(CpCACHEintr), CpCACHEwait
 	ISB
 
 	MOVW	R3, CPSR			/* splx */
@@ -199,7 +199,7 @@
  */
 TEXT mmuinvalidate(SB), 1, $-4
 	MOVW	$0, R0
-	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
+	MCR	P(CpSC), 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
 	BARRIERS
 	RET
 
@@ -208,7 +208,7 @@
  *   invalidate tlb entry for virtual page address va, ASID 0
  */
 TEXT mmuinvalidateaddr(SB), 1, $-4
-	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinvse
+	MCR	P(CpSC), 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinvse
 	BARRIERS
 	RET
 
@@ -219,7 +219,7 @@
 TEXT cachedwbinv(SB), 1, $-4
 	DSB
 	MOVW	$0, R0
-	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEwbi), CpCACHEall
+	MCR	P(CpSC), 0, R0, C(CpCACHE), C(CpCACHEwbi), CpCACHEall
 	RET
 
 /*
@@ -261,8 +261,8 @@
 TEXT cacheuwbinv(SB), 1, $-4
 	BARRIERS
 	MOVW	$0, R0
-	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEwbi), CpCACHEall
-	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
+	MCR	P(CpSC), 0, R0, C(CpCACHE), C(CpCACHEwbi), CpCACHEall
+	MCR	P(CpSC), 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
 	RET
 
 /*
@@ -270,5 +270,5 @@
  */
 TEXT cacheiinv(SB), 1, $-4
 	MOVW	$0, R0
-	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
+	MCR	P(CpSC), 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
 	RET
diff -Nru /n/sources/plan9/sys/src/9/bcm/main.c /sys/src/9/bcm/main.c
--- /n/sources/plan9/sys/src/9/bcm/main.c	Fri Sep 20 16:38:39 2013
+++ /sys/src/9/bcm/main.c	Sun Dec 15 17:36:59 2019
@@ -239,6 +239,7 @@
 	confinit();		/* figures out amount of memory */
 	xinit();
 	uartconsinit();
+	rdbinit();
 	screeninit();
 
 	print("\nPlan 9 from Bell Labs\n");
@@ -500,15 +501,11 @@
 }
 
 static void
-shutdown(int ispanic)
+shutdown(void)
 {
 	int ms, once;
 
 	lock(&active);
-	if(ispanic)
-		active.ispanic = ispanic;
-	else if(m->machno == 0 && (active.machs & (1<<m->machno)) == 0)
-		active.ispanic = 0;
 	once = active.machs & (1<<m->machno);
 	active.machs &= ~(1<<m->machno);
 	active.exiting = 1;
@@ -529,9 +526,10 @@
  *  exit kernel either on a panic or user request
  */
 void
-exit(int code)
+exit(int ispanic)
 {
-	shutdown(code);
+	if(!ispanic)
+		shutdown();
 	splfhi();
 	archreboot();
 }
@@ -558,7 +556,7 @@
 
 	print("starting reboot...");
 	writeconf();
-	shutdown(0);
+	shutdown();
 
 	/*
 	 * should be the only processor running now
diff -Nru /n/sources/plan9/sys/src/9/bcm/mkfile /sys/src/9/bcm/mkfile
--- /n/sources/plan9/sys/src/9/bcm/mkfile	Mon Mar 25 22:38:21 2013
+++ /sys/src/9/bcm/mkfile	Tue Dec 17 14:44:47 2019
@@ -70,7 +70,7 @@
 	/$objtype/lib/libmp.a\
 	/$objtype/lib/libc.a\
 
-9:V: $p$CONF s$p$CONF
+9:V: $p$CONF s$p$CONF u$p$CONF
 
 $p$CONF:DQ:	$CONF.c $OBJ $LIB mkfile
 	$CC $CFLAGS '-DKERNDATE='`{date -n} $CONF.c
@@ -82,6 +82,10 @@
 	$LD -l -o $target -R4096 -T$loadaddr $OBJ $CONF.$O $LIB
 	size $target
 
+u$p$CONF:DQ:	$CONF.$O $OBJ $LIB
+	echo '# linking u-boot image'
+	$LD -l -o $target -H8 -R4096 -T$loadaddr $OBJ $CONF.$O $LIB
+
 $p$CONF.gz:D:	$p$CONF
 	gzip -9 <$p$CONF >$target
 
@@ -89,10 +93,10 @@
 
 install:V: /$objtype/$p$CONF
 
-/$objtype/$p$CONF:D: $p$CONF s$p$CONF
-	cp -x $p$CONF s$p$CONF /$objtype/ &
+/$objtype/$p$CONF:D: $p$CONF s$p$CONF u$p$CONF
+	cp -x $p$CONF s$p$CONF u$p$CONF /$objtype/ &
 	for(i in $EXTRACOPIES)
-		{ 9fs $i && cp $p$CONF s$p$CONF /n/$i/$objtype && echo -n $i... & }
+		{ 9fs $i && cp $p$CONF s$p$CONF u$p$CONF /n/$i/$objtype && echo -n $i... & }
 	wait
 	echo
 	touch $target
@@ -130,3 +134,6 @@
 	 xd -1x reboot.out |
 		sed -e '1,2d' -e 's/^[0-9a-f]+ //' -e 's/ ([0-9a-f][0-9a-f])/0x\1,/g'
 	 echo '};'} > reboot.h
+
+%.clean:V:
+	rm -f $stem.c [9bz]$stem [9bz]$stem.gz s[9bz]$stem u[9bz]$stem boot$stem.*
diff -Nru /n/sources/plan9/sys/src/9/bcm/rebootcode.s /sys/src/9/bcm/rebootcode.s
--- /n/sources/plan9/sys/src/9/bcm/rebootcode.s	Fri Dec 28 13:39:36 2012
+++ /sys/src/9/bcm/rebootcode.s	Wed Jul  3 03:29:19 2013
@@ -25,9 +25,9 @@
 	BL	cachesoff(SB)
 
 	/* turn off mmu */
-	MRC	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
+	MRC	P(CpSC), 0, R1, C(CpCONTROL), C(0), CpMainctl
 	BIC	$CpCmmu, R1
-	MCR	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
+	MCR	P(CpSC), 0, R1, C(CpCONTROL), C(0), CpMainctl
 
 	/* set up a tiny stack for local vars and memmove args */
 	MOVW	R8, SP			/* stack top just before kernel dest */
@@ -55,18 +55,18 @@
 	/* write back and invalidate caches */
 	BARRIERS
 	MOVW	$0, R0
-	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEwbi), CpCACHEall
-	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
+	MCR	P(CpSC), 0, R0, C(CpCACHE), C(CpCACHEwbi), CpCACHEall
+	MCR	P(CpSC), 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
 
 	/* turn caches off */
-	MRC	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
+	MRC	P(CpSC), 0, R1, C(CpCONTROL), C(0), CpMainctl
 	BIC	$(CpCdcache|CpCicache|CpCpredict), R1
-	MCR	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
+	MCR	P(CpSC), 0, R1, C(CpCONTROL), C(0), CpMainctl
 
 	/* invalidate stale TLBs before changing them */
 	BARRIERS
 	MOVW	$KZERO, R0			/* some valid virtual address */
-	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
+	MCR	P(CpSC), 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
 	BARRIERS
 
 	/* from here on, R0 is base of physical memory */
@@ -80,7 +80,7 @@
 
 	/* invalidate stale TLBs again */
 	BARRIERS
-	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
+	MCR	P(CpSC), 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
 	BARRIERS
 
 	/* relocate SB and return address to PHYSDRAM addressing */
diff -Nru /n/sources/plan9/sys/src/9/bcm/trap.c /sys/src/9/bcm/trap.c
--- /n/sources/plan9/sys/src/9/bcm/trap.c	Tue Mar 26 15:33:31 2013
+++ /sys/src/9/bcm/trap.c	Sun Jun 30 04:08:43 2013
@@ -480,13 +480,18 @@
 	uintptr l, i, v, estack;
 	u32int *p;
 	char *s;
+	extern char *kernfile;
 
 	if((s = getconf("*nodumpstack")) != nil && strcmp(s, "0") != 0){
 		iprint("dumpstack disabled\n");
 		return;
 	}
-	iprint("ktrace /kernel/path %#.8lux %#.8lux %#.8lux # pc, sp, link\n",
-		ureg->pc, ureg->sp, ureg->r14);
+	if((s = getconf("*nodumppath")) != nil && strcmp(s, "0") != 0){
+		if(s = strrchr(kernfile, '/'))
+			kernfile = ++s;
+	}
+	iprint("ktrace %s %#.8lux %#.8lux %#.8lux # pc, sp, link\n",
+		kernfile, ureg->pc, ureg->sp, ureg->r14);
 	delay(2000);
 	i = 0;
 	if(up != nil && (uintptr)&l <= (uintptr)up->kstack+KSTACK)

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